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# # old_revision [8760ae9232295422550b79f09e55122390704b3c] # new_revision [23a3e9a50b4034343e3bd217d2c225dcaec064dd] # # patch "crt0.s" # from [adfe53d34fb8bcfcb9ecc9f2824f484661f0ec94] # to [0dec978fe999503c2346f42cb3588323205db715] # ============================================================ --- crt0.s adfe53d34fb8bcfcb9ecc9f2824f484661f0ec94 +++ crt0.s 0dec978fe999503c2346f42cb3588323205db715 @@ -10,12 +10,24 @@ .equ APB_DIVIDER, 4 /* 1, 2 or 4 */ .equ UND_STACK_SIZE, 0x0004 - .equ SVC_STACK_SIZE, 0x0004 + .equ SVC_STACK_SIZE, 0x0010 .equ ABT_STACK_SIZE, 0x0004 .equ FIQ_STACK_SIZE, 0x0004 .equ IRQ_STACK_SIZE, 0x0080 .equ USR_STACK_SIZE, 0x0400 + +.global _stack_size + + .equ _stack_size, 0 + .equ _stack_size, _stack_size + UND_STACK_SIZE + .equ _stack_size, _stack_size + SVC_STACK_SIZE + .equ _stack_size, _stack_size + ABT_STACK_SIZE + .equ _stack_size, _stack_size + FIQ_STACK_SIZE + .equ _stack_size, _stack_size + IRQ_STACK_SIZE + .equ _stack_size, _stack_size + USR_STACK_SIZE + + # Processor definitions .equ Mode_USR, 0x10 @@ -69,7 +81,7 @@ vectors: b prefetch_abort_handler b data_abort_handler nop /* reserved */ - b irq_handler + ldr pc, [pc, #-0xff0] /* branch through VICVectAddr register */ b fiq_handler @@ -174,14 +186,44 @@ undefined_handler: # Undefined handlers can just spin for now undefined_handler: -swi_handler: prefetch_abort_handler: data_abort_handler: -irq_handler: fiq_handler: __back: b __back + + .equ SWI_MAX, 1 + +swi_handler: + stmfd sp!, {ip, lr} + ldr ip, [lr, #-4] + bic ip, #0xff000000 + + cmp ip, #SWI_MAX + ldmhifd sp!, {ip, pc}^ + + add ip, pc, ip, lsl #2 + ldr pc, [ip] + +swi_branch_table: + .word disable_interrupts + .word enable_interrupts + + +disable_interrupts: + mrs ip, SPSR + orr ip, ip, #I_Bit + msr SPSR_c,ip + ldmfd sp!, {ip, pc}^ + +enable_interrupts: + mrs ip, SPSR + bic ip, ip, #I_Bit + msr SPSR_c,ip + ldmfd sp!, {ip, pc}^ + + .endfunc .end